Wed . 19 Jun 2019


tensilica processor ip, tensilica audio
Tensilica is a company based in Silicon Valley in the semiconductor intellectual property core business It is now a part of Cadence Design Systems Its dataplane processors DPUs combine the strengths of CPUs and DSPs and custom logic with 10 to 100 times the performancecitation needed, making them suited for data-intensive processing tasks

Tensilica is known for its customizable microprocessor core, the Xtensa configurable processor Other products include: HiFi audio/voice DSPs with a software library of over 125 codecs from Cadence and over 55 software partners; IVP Image/Video DSP, designed to handle complex algorithms in imaging, video and computer vision; and ConnX family of baseband DSPs ranging from the dual-MAC ConnX D2 to the 64-MAC ConnX BBE64EP

Tensilica was founded in 1997 by Chris Rowen one of the founders of MIPS Technologies and was initially staffed by former employees of several other Silicon Valley processor and electronic design automation companies It employed Earl Killian, who contributed to the MIPS instruction set, as chief software architect for several years1 On March 11, 2013, Cadence Design Systems announced its intent to buy Tensilica for approximately $380 million in cash2 Cadence completed the acquisition in April 2013, with a cash outlay at closing of approximately $326 million 3


  • 1 Cadence Tensilica products
    • 11 Xtensa configurable cores
      • 111 Xtensa instruction set
      • 112 Adoption
    • 12 HiFi Audio and Voice DSP IP
      • 121 Adoption
  • 2 History
  • 3 Company name
  • 4 References
  • 5 External links

Cadence Tensilica productsedit

Cadence Tensilica develops SIP blocks to be included on the dies of products of their licensees, such as system on a chips for embedded systems, particularly in mobile, home entertainment, and communications

Xtensa configurable coresedit

An Xtensa DPU data plane processing unit can be employed as anything from a small, low-power cache-less microcontroller to a high-performance 16-way SIMD, 3-issue VLIW DSP core

IP processor vendors such as Tensilica typically offer their licensees the choice between many of the IP core's implementation details: cache size, processor bus width, data and instruction RAMs, memory management and interrupt control However, Cadence's Xtensa architecture offers a key differentiating feature, a user-customizable instruction set

Using the supplied customization tools, customers can extend the Xtensa base instruction set by adding new user-defined instructions Extensions can include SIMD instructions, new register files, and additional data transfer interfaces for multiprocessor communication After the final processor configuration is made and submitted, Cadence's processor generator service builds the configured Xtensa IP core, processor design kit, and software development kit This process is highly automated so designers can quickly experiment with different instruction additions, testing the performance improvements and power trade-offs of the various alternatives

The processor kit contains items necessary to integrate the configured IP into the customer's chip design environment: the core's hardware description in synthesizeable RTL or physical post-layout form, timing & I/O constraints, requirements for technology-specific RAMs/caches/FIFOs The software kit is built on the Eclipse-based integrated development environment, and uses a GNU Compiler Collection-derived tool-chain: C/C++ compiler, assembler, linker, debugger An instruction set simulator enables customers to begin application development before actual hardware is available

Xtensa instruction setedit

The Xtensa instruction set is designed to meet the diverse requirements of dataplane processing This 32-bit architecture features a compact 16- and 24-bit instruction set with modeless switching for maximum power efficiency and performance The base instruction set has 80 RISC instructions and includes a 32-bit ALU, up to 64 general-purpose 32-bit registers, and six special-purpose registers


AMD's TrueAudio and Unified Video Decoder are ASICs based on Xtensa

HiFi Audio and Voice DSP IPedit

Simplified block diagrams of HiFi Audio Engine and Xtensa LX
  • HiFi Mini Audio DSP — The smallest, lowest power DSP core for always-listening voice trigger and voice recognition
  • HiFi 2 Audio DSP — This highly efficient DSP core provides the lowest power MP3 audio processing
  • HiFi EP Audio DSP — A superset of HiFi 2 with advanced optimizations for DTS Master Audio, improved voice pre- and post-processing, and improved cache memory subsystem
  • HiFi 3 Audio DSP — Full 32-bit processing makes this DSP super efficient for many of the audio enhancement algorithms, wideband voice codecs, and multi-channel audio
  • New - The HiFi 4 DSP - 2X HiFi 3 performance for DSP intensive applications including emerging multi-channel object-based audio standards


AMD TrueAudio, found eg in the PlayStation 4, in "Kaveri" desktop APUs and in a very few of AMD's graphics cards, is based on the Cadence Tensilica HiFi EP Audio DSP

The ESP8266 and ESP32 embedded Wi-Fi chip utilises the Xtensa as its main CPU core

Microsoft HoloLens uses special custom-designed TSMC-fabricated 28nm coprocessor that has 24 Tensilica DSP cores It has around 65 million logic gates, 8MB of SRAM, and an additional layer of 1GB of low-power DDR3 RAM4


  • In 1997 Tensilica was founded by Chris Rowen
  • In 2002 Tensilica released support for flexible length instruction encodings, known as FLIX
  • In 2013 Cadence Design Systems acquired Tensilica

Company nameedit

The brand name Tensilica is a combination of the word tensile, meaning capable of being extended, and the word silicon, the element of which integrated circuits are primarily made


  1. ^ "Technical Advisory Board" Stretch 2010-11-26 Retrieved 2010-11-26 Earl He is the former Chief Architect of Tensilica and Silicon Graphics MIPS division,  
  2. ^ "Cadence to Acquire Tensilica"
  3. ^ Source: http://ipcadencecom/news/432/330/Cadence-Reports-First-Quarter-2013-Financial-Results-and-Completes-Acquisition-of-Tensilica
  4. ^ http://wwwtheregistercouk/2016/08/22/microsoft_hololens_hpu/

External linksedit

  • Official website
  • Linux on Xtensa
  • Cadence to acquire Tensilica

tensilica audio, tensilica cadence, tensilica dsp core, tensilica embedded systems, tensilica inc, tensilica l106, tensilica processor ip, tensilica toolchain, tensilica vision, tensilica xtensa

Tensilica Information about


  • user icon

    Tensilica beatiful post thanks!


Tensilica viewing the topic.
Tensilica what, Tensilica who, Tensilica explanation

There are excerpts from wikipedia on this article and video

Random Posts

La Porte, Indiana

La Porte, Indiana

La Porte French for "The Door" is a city in LaPorte County, Indiana, United States, of which it is t...
Fernando Montes de Oca Fencing Hall

Fernando Montes de Oca Fencing Hall

The Fernando Montes de Oca Fencing Hall is an indoor sports venue located in the Magdalena Mixhuca S...
My Everything (The Grace song)

My Everything (The Grace song)

"My Everything" was Grace's 3rd single under the SM Entertainment, released on November 6, 2006 Unli...
Turkish Straits

Turkish Straits

The Turkish Straits Turkish: Türk Boğazları are a series of internationally significant waterways in...