PA-RISC


PA-RISC is an instruction set architecture ISA developed by Hewlett-Packard As the name implies, it is a reduced instruction set computer RISC architecture, where the PA stands for Precision Architecture The design is also referred to as HP/PA for Hewlett Packard Precision Architecture

The architecture was introduced on 26 February 1986, when the HP 3000 Series 930 and HP 9000 Model 840 computers were launched featuring the first implementation, the TS112

PA-RISC has been succeeded by the Itanium originally IA-64 ISA, jointly developed by HP and Intel3 HP stopped selling PA-RISC-based HP 9000 systems at the end of 2008 but supported servers running PA-RISC chips until 20134

Contents

  • 1 History
  • 2 CPU specifications
  • 3 See also
  • 4 References
  • 5 External links

Historyedit

In the late 1980s, HP was building four series of computers, all based on CISC CPUs One line was the IBM PC compatible Intel i286-based Vectra Series, started in 1986 All others were non-Intel systems One of them was the HP Series 300 of Motorola 68000-based workstations, another Series 200 line of technical workstations based on a custom silicon on sapphire SOS chip design, the SOS based 16-bit HP 3000 classic series, and finally the HP 9000 Series 500 minicomputers, based on their own 16 and 32-bit FOCUS microprocessor HP planned to use PA-RISC to move all of their non-PC compatible machines to a single RISC CPU family

Precision Architecture was introduced in 1986 It had thirty-two 32-bit integer registers and sixteen 64-bit floating-point registers The number of floating-point registers was doubled in the 11 version to 32 once it became apparent that 16 were inadequate and restricted performance The architects included Allen Baum, Hans Jeans, Michael J Mahon, Ruby Bei-Loh Lee, Russel Kao, Steve Muchnick, Terrence C Miller, David Fotland, and William S Worley5

The first implementation was the TS1, a central processing unit built from discrete transistor-transistor logic 74F TTL devices Later implementations were multi-chip VLSI designs fabricated in NMOS processes NS1 and NS2 and CMOS CS1 and PCX6 They were first used in a new series of HP 3000 machines in the late 1980s – the 930 and 950, commonly known at the time as Spectrum systems, the name given to them in the development labs These machines ran MPE/iX The HP 9000 machines were soon upgraded with the PA-RISC processor as well, running the HP-UX version of UNIX

Other operating systems ported to the PA-RISC architecture include Linux, OpenBSD, NetBSD and NEXTSTEP

An interesting aspect of the PA-RISC line is that most of its generations have no Level 2 cache Instead large Level 1 caches are used, formerly as separate chips connected by a bus, and now integrated on-chip Only the PA-7100LC and PA-7300LC had L2 caches Another innovation of the PA-RISC was the addition of vectorized instructions SIMD in the form of MAX, which were first introduced on the PA-7100LC

Precision RISC Organization, an industry group led by HP, was founded in 1992, to promote the PA-RISC architecture Members included Hitachi, Redbrick Software, Allegro Consultants, Mitsubishi, NEC, OKI and Stratus

The ISA was extended in 1996 to 64 bits, with this revision named PA-RISC 20 PA-RISC 20 also added fused multiply–add instructions, which help certain floating-point intensive algorithms, and the MAX-2 SIMD extension, which provides instructions for accelerating multimedia applications The first PA-RISC 20 implementation was the PA-8000, which was introduced in January 1996

CPU specificationsedit

Model    Marketing name Year Frequency MHz Memory Bus MB/s Process µm Transistors millions Die size mm² Power W Dcache kB Icache kB L2 cache MB ISA Notes
TS-1 1986 8 10
CS-1 1987 8 16 0164 7293 1 025 10 7
NS-1 1987 25/30 15 0144 7056 10 8
NS-2 1989 275/30 15 0183 196 27 512 512 10 9
PCX 1990 10
PCX-S PA-7000 1991 66 10 058 2016 256 256 11a
PCX-T PA-7100 1992 33–100 08 085 196 2048 1024 11b
PCX-T PA-7150 1994 125 08 085 196 2048 1024 11b
PCX-T' PA-7200 1994 120 960 055 126 210 30 1024 2048 11c
PCX-L PA-7100LC 1994 60–100 075 09 2016 7–11 1 2 11d
PCX-L2 PA-7300LC 1996 132–180 05 92 2601 64 64 0–8 11e
PCX-U PA-8000 1996 160–180 960 05 38 33768 1024 1024 20
PCX-U+ PA-8200 1997 200–240 960 05 38 33768 2048 2048 20
PCX-W PA-8500 1998 300–440 1920 025 140 467 1024 512 20 10
PCX-W+ PA-8600 2000 360–550 1920 025 140 467 1024 512 20 10
PCX-W2 PA-8700+ 2001 625–875 1920 018 186 304 <71@15 V 1536 768 20
Mako PA-8800 2003 800–1000 6400 013 300 361 768/core 768/core 0 or 32 20
Shortfin PA-8900 2005 800–1100 6400 013 768/core 768/core 64 20

See alsoedit

  • Hombre chipset – A PA-7150-based chipset with a complete multimedia system for Commodore-Amiga

Referencesedit

  1. ^ "One Year Ago" 26 February 1987 Computer Business Review
  2. ^ Hewlett-Packard Company September 1987 Hewlett-Packard Journal 38 9: p 3
  3. ^ HP Completes Its PA-RISC Road Map With Final Processor Upgrade - PA-RISC Processor
  4. ^ How long will HP continue to support HP 9000 systems
  5. ^ Smotherman, Mark 2 July 2009 Recent Processor Architects
  6. ^ Paul Weissmann "Early PA-RISC Systems"
  7. ^ Marston, A et al 1987 "A 32b CMOS single-chip RISC type processor" ISSCC Digest of Technical Papers pp 28–29
  8. ^ Yetter, J et al 1987 "A 15 MIPS 32b Microprocessor" ISSCC Digest of Technical Papers
  9. ^ Boschma, Brian D et al 1989 "A 30 MIPS VLSI CPU" ISSCC Digest of Technical Papers pp 82–83, 299
  10. ^ a b "HP L1000 & L2000 rp5400/rp5450 Servers", openpanet

External linksedit

  • LostCircuits Hewlett Packard PA8800 RISC Processor overview
  • HP's documentation – page down for PA-RISC, architecture PDFs available
  • OpenPAnet Comprehensive PA-RISC chip and computer information
  • chipdborg Images of different PA-RISC processors


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