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openrisc 1000, openrisc altera
OpenRISC is a project to develop a series of open source instruction set architectures based on established reduced instruction set computing RISC principles It is the original flagship project of the OpenCores community

The first and currently only architectural description is for the OpenRISC 1000, describing a family of 32 and 64-bit processors with optional floating point and vector processing support,1 and the OpenRISC 1200 implementation of this was designed by Damjan Lampret in 2000, written in the Verilog hardware description language23

The hardware design was released under the GNU Lesser General Public License LGPL, while the models and firmware were released under the GNU General Public License GPL

A reference SoC implementation based on the OpenRISC 1200 was developed, known as ORPSoC the OpenRISC Reference Platform System-on-Chip A number of groups have demonstrated ORPSoC and other OR1200 based designs running on FPGAs,45 and there have been a number of commercial derivatives produced

OpenCores has always been a commercially owned organization In 2015, the core active users of OpenCores established the independent Free and Open Source Silicon Foundation FOSSi, and registered the libreCoresorg website, as the basis for all future development, independent of commercial control


  • 1 Instruction set
  • 2 Implementations
    • 21 Commercial implementations
    • 22 Academic and non-commercial use
  • 3 Toolchain support
  • 4 Operating system support
    • 41 Linux support
    • 42 RTOS support
  • 5 QEMU support
  • 6 See also
  • 7 References
  • 8 External links

Instruction setedit

The instruction set is a reasonably simple MIPS-like traditional RISC using a 3-operand load-store architecture, with 16 or 32 general-purpose registers and a fixed 32-bit instruction length The instruction set is mostly identical between the 32 and 64 bit versions of the specification, the main difference being the register width 32 or 64 bits and page table layout The OpenRISC specification includes all features common to modern desktop/server processors: a supervisor mode and virtual memory system, optional read, write and execute control for memory pages, and instructions for synchronization and interrupt handling between multiple processors

Another notable feature is a rich set of SIMD instructions intended for digital signal processing


OpenRISC prototyped on Flex FPGA dev board, running uClinux

Most implementations are on FPGAs which give the possibility to iterate on the design at the cost of performance

As the OpenRISC 1000 is now considered stable, ORSoC launched a crowd-funding project trying to build a cost-efficient ASIC to get improved performance ORSoC faced criticism for this from the community The project never reached the goal

As of January 2017, no open-source ASIC has been produced yet

Commercial implementationsedit

Several commercial organizations have developed derivatives of the OpenRISC 1000 architecture, including the ORC32-1208 from ORSoC and the BA12, BA14 and BA22 from Beyond Semiconductor Dynalith Systems provide the iNCITE FPGA prototyping board, which is capable of running both the OpenRISC 1000 and BA12 Flex and Jennic Limited manufactured the OpenRISC as part of an ASIC Samsung use the OpenRISC 1000 in their DTV system-on-chips SDP83 B-Series, SDP92 C-Series, SDP1001/SDP1002 D-Series, SDP1103/SDP1106 E-Series6 Allwinner Technology are reported to use an OpenRISC core in their AR100 power controller, which forms part of the A31 ARM-based SoC7

Cadence Design Systems have started using OpenRISC as a reference architecture in documenting tool chain flows for example the UVM reference flow, now contributed to Accellera8

TechEdSat, the first NASA OpenRISC architecture based Linux computer launched in July 2012, and was deployed in October 2012 to the International Space Station with hardware provided, built, and tested by ÅAC Microtec and ÅAC Microtec North America910

Academic and non-commercial useedit

Being open source, OpenRISC has proved popular in academic and hobbyist circles For example, Stefan Wallentowitz and his team at the Institute for Integrated Systems at the Technische Universität München have used OpenRISC in research into multicore architectures11 The Open Source Hardware User Group in the UK has on two occasions1213 run sessions on OpenRISC, while hobbyist Sven-Åke Andersson has written a comprehensive blog on OpenRISC for beginners,14 which attracted the interest of EE Times15 Sebastian Macke has implemented jor1k, an OpenRISC 1000 emulator in JavaScript, running Linux with X Window System and Wayland support16

Toolchain supportedit

The OpenRISC community have ported the GNU toolchain to OpenRISC to support development in C and C++ Using this toolchain the newlib, uClibc, musl as of release 114 and glibc libraries have been ported to the processor Dynalith provides OpenIDEA, a graphical development environment based on this toolchain A project to port LLVM to the OpenRISC 1000 architecture started in early 2012 project page

The OR1K project provides an instruction set simulator, or1ksim The flagship implementation, the OR1200, is a register-transfer level RTL model in Verilog HDL, from which a SystemC-based cycle-accurate model can be built in ORPSoC A high speed model of the OpenRISC 1200 is also available through the Open Virtual Platforms OVP initiative set up by Imperas

Operating system supportedit

Linux supportedit

The mainline Linux kernel gained support for OpenRISC in version 3117 The implementation merged in this release is the 32-bit OpenRISC 1000 family or1k18 Previously OpenRISC 1000 architecture, but this has now been superseded by the mainline port

RTOS supportedit

A number of real-time operating systems have been ported to OpenRISC, including RTEMS, FreeRTOS and eCos

QEMU supportedit

Since version 12 19 QEMU supports emulating OpenRISC platforms

See alsoedit

  • Free software portal
  • Amber processor core, ARM-Compatible OpenCores Project
  • Free and Open Source Silicon Foundation
  • OpenRISC 1200
  • OVPsim, Open Virtual Platforms
  • OpenSPARC
  • LEON
  • LatticeMico32
  • RISC-V


  1. ^ Damjan Lampret et al, "OpenRISC 1000 Architecture Manual", Architecture Version 10, Document Revision 0, December 5, 2012 Available from the OpenCores website 1
  2. ^ Interview with OpenRISC designer Damjan Lampret, published online in EE Times in February 2000 2
  3. ^ Interview with OpenRISC designer Damjan Lampret, on the cover of February 2000 edition of EE Times3
  4. ^ Patrick Pelgrims, Tom Tierens and Dries Driessens, "Basic Custom OpenRISC System Hardware Tutorial: Embedded system design based upon Soft- and Hardcore FPGA’s", De Nayer Instituut, Hogeschool voor Wetenschap & Kunst, 2004 Available online 4
  5. ^ Xiang Li and Lin Zuo, "Open source embedded platform based on OpenRISC and DE2-70", Masters dissertation, SoC program, KTH, Sweden Available online 5
  6. ^ Samsung Open Source Release Center, follow the links → TV & VIDEO → TV → DTV → ETC → OR1200zip
  7. ^ Linux-sunxi project community wiki page on the AR100 controller Retrieved on 20 July 2013
  8. ^ UVM Reference Flow, Accellera website undated
  9. ^ Post to the openrisc mailing lists at listsopenriscnet on 8 April 2012 by Fredrick Bruhn, CEO of ÅAC Microtec
  10. ^ Press release 11 October 2012, ÅAC Microtec AB
  11. ^ Multicore Architecture and Programming Model Co-Optimization MAPCO, Stefan Wallentowitz, Thomas Wild and Andreas Herkersdorf Research poster at the Sixth International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems ACACES, Terrassa Barcelona, Spain, 11–17 July 2010
  12. ^ Chips Programmable Logic, Computer Conservation with FPGAs, OpenCores & OpenRISC 1000 OSHUG meeting #9, Skills Matter, 116-120 Goswell Road, London, 21 April 2011
  13. ^ Practical System-on-Chip Program your own open source FPGA SoC OSHUG meeting #17, Centre for Creative Collaboration, 16 Acton Street, London, 29 March 2012
  14. ^ OpenRISC 1200 soft processor Blog post by Sven-Åke Andersson, 2 March 2012
  15. ^ Comparing four 32-bit soft processor cores Clive Maxfield, EE Times, 3 May 2012
  16. ^ OpenRISC Emulator In JavaScript Can Run Wayland
  17. ^ "gitkernelorg - linux/kernel/git/torvalds/linux-26git/tree - arch/openrisc/" gitkernelorg Retrieved 2011-10-17 
  18. ^ "Linux 31" Kernel Newbies Retrieved 2011-10-17 
  19. ^ QEMU Changelog 12

External linksedit

  • Official website
  • Open Source Semiconductor Core Licensing, 25 Harvard Journal of Law & Technology 131 2011 Article analyzing the law, technology and business of open source semiconductor cores
  • Beyond Semiconductor commercial fabless semiconductor company founded by the developers of OpenRISC
  • Dynalith Systems company website
  • Imperas company website
  • Flex company website
  • Jennic company website
  • Eetimes article
  • OpenRISC tutorial
  • jor1k OpenRISC 1000 emulator in JavaScript

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