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MicroBlaze

micro blaze, micro blaze creations
The MicroBlaze is a soft microprocessor core designed for Xilinx FPGAs from Xilinx As a soft-core processor, MicroBlaze is implemented entirely in the general-purpose memory and logic fabric of Xilinx FPGAs

Contents

• 1 Overview
• 2 EDK
• 3 Open source
• 4 Clones
• 5 Other soft processors
• 6 See also
• 7 References
• 8 External links

Overviewedit

In terms of its instruction set architecture, MicroBlaze is similar to the RISC-based DLX architecture described in a popular computer architecture book by Patterson and Hennessy With few exceptions, the MicroBlaze can issue a new instruction every cycle, maintaining single-cycle throughput under most circumstances

The MicroBlaze has a versatile interconnect system to support a variety of embedded applications MicroBlaze's primary I/O bus, the CoreConnect PLB bus, is a traditional system-memory mapped transaction bus with master/slave capability A newer version of the MicroBlaze, supported in both Spartan-6 and Virtex-6 implementations, as well as the 7-Series, supports the AXI specification The majority of vendor-supplied and third-party IP interface to PLB directly or through an PLB to OPB bus bridge For access to local-memory FPGA RAM, MicroBlaze uses a dedicated LMB bus, which reduces loading on the other buses User-defined coprocessors are supported through a dedicated FIFO-style connection called FSL Fast Simplex Link The coprocessors interface can accelerate computationally intensive algorithms by offloading parts or the entirety of the computation to a user-designed hardware module

Many aspects of the MicroBlaze can be user configured:cache size, pipeline depth 3-stage or 5-stage, embedded peripherals, memory management unit, and bus-interfaces can be customized The area-optimized version of MicroBlaze, which uses a 3-stage pipeline, sacrifices clock frequency for reduced logic area The performance-optimized version expands the execution pipeline to 5 stages, allowing top speeds of 210 MHz on Virtex-5 FPGA family Also, key processor instructions which are rarely used but more expensive to implement in hardware can be selectively added/removed ie multiply, divide, and floating point operations This customization enables a developer to make the appropriate design trade-offs for a specific set of host hardware and application software requirements

With the memory management unit, MicroBlaze is capable of hosting operating systems requiring hardware-based paging and protection, such as the Linux kernel Otherwise it is limited to operating systems with a simplified protection and virtual memory model, eg FreeRTOS or Linux without MMU support MicroBlaze's overall throughput is substantially less than a comparable hardened CPU core such as the PowerPC440 in the Virtex-5

EDKedit

Xilinx's EDK Embedded Development Kit is the development package for building MicroBlaze and PowerPC or ARM - see Zynq embedded processor systems in Xilinx FPGAs Hosted in the Eclipse IDE, the project manager consists of two separate environments:XPS and SDK

Designers use XPS Xilinx Platform Studio to configure and build the hardware specification of their embedded system processor core, memory-controller, I/O peripherals, etc The XPS converts the designer's platform specification into a synthesizeable RTL description Verilog or VHDL, and writes a set of scripts to automate the implementation of the embedded system from RTL to the bitstream-file For the MicroBlaze core, the EDK normally generates an encrypted non human-readable netlist, but the processor description written in VHDL can be purchased from Xilinx

The SDK handles the software that will execute on the embedded system Powered by the GNU toolchain GNU Compiler Collection, GNU Debugger, the SDK enables programmers to write, compile, and debug C/C++ applications for their embedded system Xilinx includes a cycle-accurate instruction set simulator ISS, giving programmers the choice of testing their software in simulation, or using a suitable FPGA-board to download and execute on the actual system

Purchasers of EDK or ISE Design Suite Embedded EditionIDS are granted a perpetual license to use MicroBlaze in Xilinx FPGAs with no recurring royalties The license does not grant the right to use MicroBlaze outside of Xilinx's devices, which must be negotiated directly with Xilinx

Alternative compilers and development tools have been made available from Altium but an EDK installation and license is still required

Open sourceedit

In June, 2009, MicroBlaze became the first soft-CPU architecture to be merged into the mainline Linux kernel source tree This work was performed by Michal Simek and supported by PetaLogix and Xilinx

As of September 2009, MicroBlaze GNU tools support is also being contributed to the Free Software Foundation's mainline repositories Support for MicroBlaze is included in GCC releases starting with version 461

Clonesedit

• aeMB, implemented in Verilog, LGPL license
• OpenFire subset, implemented in Verilog, MIT license
• MB-Lite, implemented in VHDL, LGPL license
• MB-Lite+, implemented in VHDL, LGPL license
• myBlaze, implemented in MyHDL, LGPL license
• SecretBlaze, implemented in VHDL, GPL license

Other soft processorsedit

• Nios II
• TSK3000
• Xtensa
• LatticeMico32

See alsoedit

• OpenCores - a home for many open source soft processor projects
• PicoBlaze

Referencesedit

1. ^ "GCC 46 Release Series Changes, New Features, and Fixes" 2011-03-15 Retrieved 2011-03-15 Support has been added for the Xilinx MicroBlaze softcore processor microblaze-elf embedded target 

External linksedit

• MicroBlaze on Xilinx website
• PetaLogix - MicroBlaze kernel maintainers and commercial services PetaLinux
• uCLinux - uClinux-dist for Microblaze, kernel 2630
• MicroBlaze Embedded Linux support from LynuxWorks BlueCat Linux
• Linux and U-BOOT for Microblaze CPU - Michal Simek - maintainer
• MicroBlaze-Based Introduction To Computer Architecture and Assembly Language UARK
• MicroBlaze managed forum
• Running eCos RTOS on Microblaze
• Designing an embedded system using MicroBlaze RTE

v e Reduced instruction set computing RISC processor architectures
Active	Altera Nios II Analog Devices Blackfin ARC ARM Atmel AVR Atmel AVR32 DLX eSi-RISC M32R LatticeMico8 LatticeMico32 Meta MIPS OpenRISC Power PowerPC RISC-V S+core Sunway SPARC Renesas SuperH Unicore Xilinx MicroBlaze Xilinx PicoBlaze XMOS XCore XS1 VISC Mill
Historic	AMD Am29000 Apollo PRISM Berkeley RISC Clipper CRISP DEC Alpha DEC Prism Intel i860 Intel i960 Motorola 88000 PA-RISC ROMP

v e Soft microprocessor
LatticeMico8 LatticeMico32 LEON MicroBlaze Nios Nios II OpenRISC OpenSPARC PicoBlaze RISC5

v e Programmable logic
Concepts	ASIC SOC FPGA Logic block CPLD EPLD PLA PAL GAL PSoC Reconfigurable computing Xputer Soft microprocessor Circuit underutilization
Languages	Verilog A AMS VHDL AMS VITAL SystemVerilog DPI SystemC AHDL Handel-C PSL UPF PALASM ABEL CUPL OpenVera C to HDL Flow to HDL MyHDL JHDL ELLA
Companies	Accellera Actel Achronix AMD Aldec Altera Atmel Cadence Cypress Duolog Forte Intel Lattice National Mentor Graphics Microsemi Signetics Synopsys Magma Virage Logic Texas Instruments Tabula Xilinx
Products	Hardware iCE Stratix Virtex Software Altera Quartus Xilinx ISE Xilinx Vivado ModelSim VTR Simulators IP Proprietary ARC LEON LatticeMico8 MicroBlaze PicoBlaze Nios Nios II Open-source LatticeMico32 OpenCores OpenRISC 1200 RISC-V JOP

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