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makefile example, makefile
A makefile is a file containing a set of directives used with the make build automation tool


  • 1 Overview
  • 2 Operating system
    • 21 Unix-like
    • 22 Microsoft Windows
  • 3 Contents
  • 4 Rules
  • 5 Execution
  • 6 Example
  • 7 References


Most often, the makefile directs make on how to compile and link a program Using C/C++ as an example, when a C/C++ source file is changed, it must be recompiled If a header file has changed, each C/C++ source file that includes the header file must be recompiled to be safe Each compilation produces an object file corresponding to the source file Finally, if any source file has been recompiled, all the object files, whether newly made or saved from previous compilations, must be linked together to produce the new executable program1 These instructions with their dependencies are specified in a makefile If none of the files that are prerequisites have been changed since the last time the program was compiled, no actions take place For large software projects, using Makefiles can substantially reduce build times if only a few source files have changed

Operating systemedit


Makefiles originated on Unix like systems and are still a primary software build mechanism in such environments

Microsoft Windowsedit

Windows supports a variation of makefiles with its nmake utility Standard Unix like makefiles can be executed in Windows in a Cygwin environment


Makefiles contain five kinds of things: explicit rules, implicit rules, variable definitions, directives, and comments

  • An explicit rule says when and how to remake one or more files, called the rule's targets It lists the other files that the targets depend on, called the prerequisites of the target, and may also give a recipe to use to create or update the targets
  • An implicit rule says when and how to remake a class of files based on their names It describes how a target may depend on a file with a name similar to the target and gives a recipe to create or update such a target
  • A variable definition is a line that specifies a text string value for a variable that can be substituted into the text later
  • A directive is an instruction for make to do something special while reading the makefile such as reading another makefile
  • ‘#’ in a line of a makefile starts a comment It and the rest of the line are ignored


A makefile consists of “rules” in the following form:

target: dependencies system commands

A target is usually the name of a file that is generated by a program; examples of targets are executable or object files A target can also be the name of an action to carry out, such as "clean"

A dependency also called prerequisite is a file that is used as input to create the target A target often depends on several files However, the rule that specifies a recipe for the target need not have any prerequisites For example, the rule containing the delete command associated with the target "clean" does not have prerequisites

The system commands also called recipe is an action that make carries out A recipe may have more than one command, either on the same line or each on its own line Note the use of meaningful indentation in specifying commands; also note that the indentation must consist of a single <tab> character


A makefile is executed with the make command, eg make options target1 target2 By default, when make looks for the makefile, if a makefile name was not included as a parameter, it tries the following names, in order: makefile and Makefile1


Here is a simple makefile that describes the way an executable file called edit depends on four object files which, in turn, depend on four C source and two header files

edit : maino kbdo commando displayo cc -o edit maino kbdo commando displayo maino : mainc defsh cc -c mainc kbdo : kbdc defsh commandh cc -c kbdc commando : commandc defsh commandh cc -c commandc displayo : displayc defsh cc -c displayc clean : rm edit maino kbdo commando displayo

To use this makefile to create the executable file called edit, type make To use this makefile to delete the executable file and all the object files from the directory, type make clean


  1. ^ a b "POSIX Target Rules" 

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Makefile Information about


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    Makefile beatiful post thanks!


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